The present invention relates generally to the semiconductor circuitry art. More particularly, the present invention relates to a technique for controlling the current drawn through a semiconductor memory device during high speed operation.
More particularly, in the operation of a dynamic random access memory (DRAM), considerable power supply current surges may be generated. These typically result from the large capacitance associated with the bit lines, along which memory cells are located, which capacitance must be overcome during charging and discharging each cycle.
In DRAMs, the logical complement RAS of a row address strobe RAS is used to define a "cycle." Such a cycle may include nominally 100 to 120 nanoseconds, during which RAS will be high for 40 nanoseconds or so. The time between the high to low edge of RAS and the next low to high edge of RAS is called the "active period." When RAS is high in DRAMs of the prior art, precharging of the bit lines will occur. During the ensuing active period, the decoders are set up to access the intended memory cell. Afterwards, but still during the active period, the sensing and restore operations occur. These terminate when RAS goes high, signalling the end of the active period.
For example, in a fast 256K CMOS DRAM there are typically 1024 pairs of bit lines, each having a capacitance of typically 800 femtofarads (fF). When midpoint sensing is employed in such a DRAM, the DRAM must move a cumulative 800 pF. of capacitance from its precharged level of V.sub.cc /2 to V.sub.cc during the time between the initiation of sensing and the termination of the active period (which ordinarily corresponds to the initiation of the precharge period).
In a typical chip active period, sensing will generally be initated approximately 30 nS. prior to termination of the active period. During this 30 nS. time frame, sense and restore signals must be supplied to a series of two or more pull-up transistors of a sense amplifier coupled to the bit lines, such as the DRAM sense amaplifier represented in FIG. 1. In a conventional DRAM design, a first sense and restore signal will turn on a relatively small pull-up transistor. Subsequent sense and restore signals will then each turn on a somewhat larger pull-up transistor or a pair of such transistors. In this fashion the amount of current drawn through the pull-up transistors into the DRAM circuits is controlled somewhat by the size of the transistor used. Also, the relative timing between the initiation of these signals will further help control the surge of current associated with turning on the transistors.
This can be better understood by reference to FIG. 1. As is well known in the art, the differential developed between bit lines 10 and 12 may be amplified by means of a flip-flop arrangement of paired P channel and N channel transistors 14, 16, 18 and 20. The sense amplifier of FIG. 1 may be turned "on" by driving a line 22 towards V.sub.cc and driving a line 24 towards ground potential. Line 22 may be raised toward V.sub.cc by turning on a set of P channel transistors represented by transistors 26 and 28. Line 24 may be driven toward ground potential by turning on a set of N channel transistors represented by transistors 30 and 32.
Traditionally, each of paired transistors 26 and 30 is a smaller device than each of paired transistors 28 and 32. These first transistors 26 and 30 will be turned on first, thereby limiting the maximum current which may surge through to the sense amplifier by the actual physical limitations on the size of transistors 26 and 30. Once these transistors have been turned on for a period of time, the large transistors 28 and 32 will be turned on to deliver a larger current to complete the sense and restore operations.
In the circuitry of FIG. 1, transistor 30 is turned on by receipt of a first sensing signal .phi..sub.s1 on a line 34. Similarly, transistor 32 is turned on by the receipt of a second sensing signal .phi..sub.s2 on a line 36. Likewise, P channel transistors 26 and 28 are turned on by the logical complements of the first and second sensing signals received on lines 38 and 40, respectively. The timing between the first and second sensing signals determines the amount of time that the smaller transistors 26 and 30 are on before the larger transistors 28 and 32 are turned on. Correspondingly, this timing determines the current which will be drawn through transistor 28 into the DRAM circuitry when it is first turned on by reducing the source to drain potential across transistor 28 at that time.
This general method of turning on transistors in a sense amplifier at differing times is used to overcome the capacitance of bit lines 10 and 12. Consider that an amount of charge corresponding to the bit line capacitance must be supplied to the circuit. This may be done by supplying a large current for a short time or a small current for a longer time. In the method described with respect to FIG. 1, the turning on of the smaller transistors such as transistors 26 and 30 first and leaving them on for a period of time causes a certain amount of charge to be transferred to bit lines 10 and 12 to overcome partially the parasitic capacitance and raise the potential at the bit lines before the larger devices 28 and 32 are turned on. Then when the larger devices are turned on, they will allow a somewhat larger current to flow and deliver additional charge to the bit lines until they have been moved from a potential of V.sub.cc /2 to V.sub.cc. Thus, a sense amplifier as illustrated in FIG. 1 may be "turned on" in stages by means of time-staggered sense and restore signals to turn on increasingly larger pull-up transistors illustrated by the two P/N transistor pairs 26/30 and 28/32. This provides a gradual increase in current instead of a relatively unmanagable current surge all at once which would result from turning on all transistor pairs together.
Conventional logic circuitry for providing such time-staggered sense and restore signals is illustrated in FIG. 2. In the conventional approach for attempting to control the current drawn through the sense amplifier, a first sensing signal .phi..sub.s1 is initiated at a time which follows the falling edge of RAS by a period of time which is dependent upon a delay time t.sub.0. The delay time t.sub.0 is the time required to set up the bit lines for sensing. This time is dependent upon the conditions in which the DRAM is operating e.g. temperature and power supply voltage.
After initiation of the first sensing signal .phi..sub.s1, a second sensing signal .phi..sub.s2 is generated after at a time which is dependent upon a delay time t.sub.1. Time t.sub.1 may be controlled typically by a series of MOS inverters as shown in FIG. 2 which interpose a delay determined by on-chip circuitry. For example, ten to twelve MOS inverters in series may be provided by the chip fabricator. When RAS goes high indicating the initiation of the precharge period, both sensing signals .phi..sub.s1 and .phi..sub.s2 are terminated (in the prior art) by means of .phi..sub.pre signal.
More particularly, in the illustrative logic circuitry of FIG. 2, the row address strobe complement signal (RAS) is received on a line 42. The RAS signal passes through inverter gates 43 to generate the .phi..sub.pre signal on a line 44. The .phi.pre signal is the same logically as the RAS signal except that it is delayed by the delay time of gates 43. The .phi.pre signal is used to enable NOR gates 46 and 48 for later generation of the first and second sensing signals. The first sensing signal .phi..sub.s1 is generated after a delay time t.sub.0 (plus the delay time of NOR gate 46); following the initiation of the .phi.pre signal. The delay time t.sub.0 is determined by the time required to set up the bit lines of the dynamic RAM, which time is represented by a delay block 50. The first sensing signal .phi..sub.s1 generated at a point 52 is supplied to the sense amplifier via line 34 (FIG. 1). The .phi..sub.s1 signal is input to an inverter 54 to generate .phi..sub.s1 the logical complement of the first sensing signal. The .phi..sub.s1 is and supplied to transistor 26 of FIG. 1 via line 38.
The second sensing signal .phi..sub.s2 is generated after a delay time t.sub.1 (plus the delay time of NOR gate 48) following the initiation of signal .phi..sub.s1. The delay time t.sub.1 is determined by a series of MOS inverters 56 to create a determinable delay between the first and second sensing signals. Thus, after the initiation of the first sensing signal, the second sensing signal will be generated at the output of NOR gate 48 and fed via line 36 (FIG. 1) to N channel transistor 32 of FIG. 1. Similarly, inverter gate 58 may be used to generate the logical complement of the second sensing signal to turn on the larger transistor 28 of FIG. 1 via line 40. Thus, in this fashion, the art has attempted to control the current surge when bit line capacitance needs to be overcome.
This prior technique has led to some major disadvantages, however. A typical DRAM will be called upon to meet its specified access times over a large range of temperature, power supply and process parameters. The 30 nS. interval between the first set of sense and restore signals .phi..sub.s1 and .phi..sub.s1 and the second set of sense and restore signals .phi..sub.s2 and .phi..sub.s2 will typically be the "worst case," or slowest timing condition. The other extreme or "best case" timing will reduce the time interval for the sense and restore signals to about 15 nS.
In the best case condition, ambient temperature is about 0.degree. C. and V.sub.cc =5.5 volts. The DRAM circuit may have to move the 800 pF. of capacitance associated with the bit lines from about 2.25 volts to about 5.5 volts in 15 nS. That requires 2600 picoCoulombs of charge to be supplied through the V.sub.cc pin. Even if it were possible to supply this amount of charge with a perfectly triangular current waveform (to minimize current surge), it would still require a current ramp rate of 45 mA. per nS. up to a maximum current peak of 350 mA. Both of these parameters are unacceptably high for the typical DRAM circuit and will tend to degrade the chip power supply. Also, peripheral circuits may fail after repeated such current surges.
Alternatively, if the DRAM is operating in its "worst case," the circuit will operate slowest. That is, when the ambient temperature is approximately 100.degree. C. and the power supply is approximately 4.5 volts, t.sub.0 will be at its maximum value. Likewise, the t.sub.1 MOS inverter delay period will be at its maximum value because of the slower operation of the inverter gates. The first sensing signal .phi..sub.s1 will be initiated well into the chip active period, and the second sensing signal .phi..sub.s2 will be generated after a relatively long delay at a time shortly before the chip active period terminates. Both of these sensing signals will be terminated at the end of the chip active period. Under these ambient conditions, the maximum current which may be generated is typically much less than would be generated under "best case" conditions. Accordingly, the delay between the first and second sensing signals need not be as long to provide the desired current stabilization. However, becuase of the delays inherent in this approach, the access time for the DRAM becomes unacceptable.
Thus, it can be seen that the method heretofore used in the art for overcoming the inherent capacitance of the bit lines under certain operating conditions would be incompatible with either the current limitations of the part or its required fast access times.
Accordingly, it is a principal object of the present invention to provide a technique for allowing desirable access times with controlled current drawn through the DRAM circuitry over a wide range of operating conditions.
It is a further object of the present invention to provide a technique for stabilizing the current through DRAM circuitry which does not allow the delay between first and second sensing signals to decrease as the circuitry operates faster, but does allow the delay between first and second sensing signals to decrease when the DRAM is operating slowest.